Vhdl-based Design and Analysis of Defect Tolerant Vlsuwsi Array Architectures

Design and analysis of reconfigurable VLSVWSI array architectures is an increasingly complicated task, especially in evaluating the impact of reconfiguration mechanisms on performance, overhead, and yield. In this paper, we present an integrated computer-aided design environment, the VAR (VHDLbased Array Reconfiguration) system, for the tasks of design, diagnosis, reconfiguration, simulation, and evaluation of an array architecture described in VHDL. VAR allows us to study fault diagnosis and reconfiguration algorithms by inserting user-defined faults into the array and then locate the faulty PES as well as simulate the actual reconfiguration process by mapping a target array onto a host array. Thus, VAR can assist the designer in evaluating different combinations of diagnosis algorithms, reconfiguration algorithms, and reconfigurable architectures.